1. Field of the Invention
The present invention relates to an embedded DisplayPort system, and more particularly, to an embedded DisplayPort system capable of implementing a panel self refresh mode and a method for controlling a panel self refresh mode.
2. Description of the Related Art
According to the recent development trend of display panels, a connection between an LVDS (Low Voltage Differential Signaling) signal and a timing controller has been replaced with an embedded DisplayPort.
The VESA (Video Electronics Standards Association) has suggested the standards of an embedded DisplayPort in a flat panel television on May 10, 2010, and the VESA Embedded DisplayPort Standard Version 1.3 has been published.
The VESA Embedded DisplayPort Standard Version 1.3 has proposed panel self refresh technology, and the panel self refresh (hereinafter, referred to as “PSR”) technology proposes a method for reducing system-level power consumption.
According to the PSR technology, when an image displayed on the screen is static during a plurality of display frames, the static image is stored in a remote frame buffer and continuously displayed in a state where a source device of an embedded DisplayPort (hereafter, referred to as “eDP”) system to transmit the image is turned off and a sink device (display panel device) of the eDP system is not turned off.
In the PSR mode, the source device of the eDP system is switched to a turn-off state. Therefore, system-level power consumption may be reduced as much as the source device is turned off.
Since the source device of the eDP system is turned off in the PSR mode, the source device does not transmit data to the sink device.
Therefore, until the PSR mode is ended, the sink device needs to generate a stream clock having the same frequency as before the PSR mode, in order to display an image stored in the remote frame buffer therein.
The eDP system uses a link symbol clock LS_CLK when the source device transmits data to the sink device.
For example, the link symbol clock LS_CLK has transmission rates of 270 M bytes/sec and 162 M bytes/sec based on one lane in a high bit rate (hereafter, referred to as “HBR”) mode and a reduced bit rate (hereafter, referred to as “RBR”) mode, respectively. Here, each of 270 M bytes/sec and 162 M bytes/sec is the speed of a clock used for data transmission between the source device and the sink device.
The sink device of the conventional eDP system receives a link symbol clock LS_CLK transmitted from the source device and stream data M and N generated by a source in a general mode in which an image displayed on the screen is not static, and recovers a stream clock required for displaying the image using the link symbol clock LS_CLK and the stream data M and N generated by the source.
In the PSR mode, however, the sink device of the eDP system does not receive a link symbol clock LS_CLK and stream data M and N from the source device because the source device is turned off.
Therefore, it is necessary to provide a method in which the sink device continuously recovers a stream clock having the same frequency as before the PSR mode, in order to display a static image in the PSR mode.
In order for the sink device to continuously recover a stream clock having the same frequency in the PSR mode, an internal or external oscillator having no difference in frequency between chips may be used in the source device and the sink device.
The eDP system may be configured in such a manner that the link symbol clock LS_CLK has a frequency of 270 MHz in the HBR mode and a frequency of 162 MHz in the RBR mode.
Therefore, when the internal or external oscillator having no difference in frequency between chips is used, the sink device may recover a stream clock using the link symbol clock LS_CLK generated by the internal or external oscillator or a clock corresponding to the link symbol clock LS_CLK as a reference clock.
That is, when the internal or external oscillator having no frequency difference between chips is used, the sink device stores stream data transmitted from the source device in a general mode. When entering the PSR mode, the sink device may recover a stream clock using the clock of the internal or external oscillator.
However, it is actually difficult to fabricate the internal oscillator having no difference in frequency between chips. Although an oscillator using an inductor-capacitor (L-C) tank with a small frequency difference is applied, there exists a frequency difference between chips. The oscillator using an L-C tank has a disadvantage in that it has a large chip size.
Furthermore, there is additionally needed a circuit for trimming the internal oscillator by comparing a link symbol clock recovered by a clock data recovery circuit and a clock generated by the internal oscillator in a general mode, in order to reduce the frequency difference between chips.
Although the clock of the internal oscillator is adjusted by the trimming circuit, there is a limit to the resolution of the trimming circuit. Therefore, it is difficult for the sink device to recover a stream clock having the same frequency as the link symbol clock LS_CLK.
Furthermore, an external oscillator such as a crystal oscillator has a constant frequency, but is expensive.
Therefore, the conventional eDP system requires a device capable of continuously recovering a stream clock having the same frequency as before the PSR mode such that the sink device displays a static image in response to the PSR mode.
Furthermore, the device to recover a stream clock in response to the PSR mode needs to be implemented at a low price and with a simple configuration.